This article was published in the April 2015 issue of Maximum PC. For more trusted reviews and feature stories, subscribe here.
Adding dimensions to evolving (and shrinking) chip technology
Three-dimensional flash memory is the latest chip technology that’s truly revolutionary and Samsung is leading the way with its 3D-NAND flash-memory cells in 500GB SSDs. Multiterabyte SSDs will soon follow. It’s the biggest news in semiconductor tech since 2011.
That was the year when Intel revolutionized digital logic by mass-producing the first microprocessors with three-dimensional finFET transistors. But it’s also causing confusion. Samsung’s 3D-NAND flash memory is completely different. Different again is a 3D-stacked chip. Heck, some folks are even confusing these innovations with 3D-graphics processors. They’re all different. But they do have one thing in common—they’re solutions for cramming more transistors into less space.
Samsung’s 850 Pro was the 3D revolution’s trailblazing SSD.
Flash memory urgently needs help because atomic-level physical limitations prevent it from getting much denser, faster, or cheaper. Whereas DRAM and SRAM cells quickly lose all their electrons when powered down, flash cells preserve data by trapping electrons in a “floating gate” (a conductive material) sandwiched between two insulators. Eventually, the trapped electrons escape, but not for years. The retention time depends on several factors, including the number of trapped electrons and whether they’re disturbed by electrical activity.
But transistors are getting so small that the number of electrons they trap is getting alarmingly low. Ten years ago, a typical NAND-flash bit cell retained about 1,000 electrons per bit. Now it’s about 50. Even worse, some flash memory stores more bits per cell by sensing multiple voltage levels. With a conventional single-level cell (SLC), only one voltage level spells the difference between a one or a zero (one bit). A multilevel cell (MLC) stores two bits by using four voltage levels. A triple-level cell (TLC) stores three bits in eight levels. The more levels, the fewer electrons per level.
Leaking only a few of those electrons can evaporate your data. Also, repeated read/write operations permanently trap some electrons, which prevents the cell from flipping between one and zero, making it useless. That’s why flash drives use wear leveling to evenly distribute the operations. To overcome these problems, 3D NAND stacks the bit cells vertically. It packs more cells into the same space without necessarily shrinking the transistors and compromising their data retention and endurance. This solution seems obvious, but the manufacturing details are devilish.
Intel’s finFETs (finned field-effect transistors) solve a different problem. A logic transistor must leak as few electrons as possible through its gate when switched to its “off” binary state. But as transistors keep getting smaller, their gates get shorter, enabling more electrons to escape. By fabricating transistors with a vertical fin rising above the chip’s surface, Intel ups the gate’s effective length without using more horizontal space. These 3D transistors aren’t stacked, as they are in 3D-NAND; they are “3D” in comparison with a conventional planar (flat) transistor.
Stacked chips are another “3D” variation. They simply pile two or more silicon die on top of each other. Usually these “3D” chips are designed to save board space in small systems like mobile phones. A 3D-graphics processor is yet another breed. It’s simply a microprocessor optimized to run 3D-graphics software. It needn’t use any of the 3D technologies described above.
Confusion arises, even among gearheads, when we use vague terms like “3D” to describe very different technologies intended to solve very different problems.
Tom Halfhill was formerly a senior editor for Byte magazine and is now an analyst for Microprocessor Report.
From maximumpc
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